Afio _ EXICR 1 (external interrupt configuration register 1)

15-0 Bits: EXTI[3:0]EXTIx(x=0-3) Configure (manually) the external interrupt input source for selecting EXTIx.

Definition: 0000(PA[x] pin), 000 1(PB[x] pin), 00 10(PC[x] pin), 001(PD [x] pin).

AFIO_EXTICR2 (external interrupt configuration register 2)

15-0 Bits: EXTI[3:0]EXTIx(x=4-7) Configure (manually) the external interrupt input source for selecting EXTIx.

Definition: 0000(PA[x] pin), 000 1(PB[x] pin), 00 10(PC[x] pin), 001(PD [x] pin).

AFIO_EXTICR3 (external interrupt configuration register 3)

15-0 bits: Exti [3: 0] EXTIx (x = 8-11) is configured (manually) to select the external interrupt input source of Extix.

Definition: 0000(PA[x] pin), 000 1(PB[x] pin), 00 10(PC[x] pin), 001(PD [x] pin).

AFIO_EXTICR4 (external interrupt configuration register 4)

15-0 bits: Exti [3: 0] EXTIx (x =12-15) configures (manually) the external interrupt input source for selecting Extix.

Definition: 0000(PA[x] pin), 000 1(PB[x] pin), 00 10(PC[x] pin), 001(PD [x] pin).

EXTI_IMR (interrupt mask register)

19-0 bits: event masking on MRx line X, definition: 0 (shielding event request from X line), 1 (on-time request from X line) Note: 19 is only used for interconnection type and reserved for other chips.

EXTI_EMR (interrupt mask register)

19-0 bits: event masking on MRx line X, definition: 0 (shielding event request from X line), 1 (on-time request from X line) Note: 19 is only used for interconnection type and reserved for other chips.

EXTI_RTSR (rising edge trigger select register)

0- 19 bit: TRx line rising edge trigger time configuration bit, definition: 0 (forbidden input line X rising edge trigger (interrupt and event), 1 (allowed input line X rising edge trigger (interrupt and time) Note: 19 bit is used for interconnection type.

EXTI_FTSR (falling edge trigger select register)

0- 19 bit: TRx line rising edge trigger time configuration bit, definition: 0 (input line X rising edge trigger is prohibited (interrupt and event), 1 (input line X rising edge trigger is allowed (interrupt and time)) Note: 19 bit is used for interconnection type.

EXTI_SWIER

19-0 bits: software interrupt on SWIERx line. When this bit is 0, writing 1 will set the corresponding suspend bit in EXTI_PR. If EXTI_IMR and EXTI_EMR allow interrupts, an interrupt will be generated at this time.

Note: By clearing the corresponding bit of EXTI_PR (write 1), the interconnection of 19 bits can be cleared and reserved for other chips.

EXTI_PR (pending register)

19-0 bits: PRx pending bit, definition: 0 (no trigger request occurred), 1 (selection trigger request occurred) Note: 19 bits are used for interconnection types and reserved for other products.

This bit is set to 1 when the selected edge event occurs on the external interrupt line. This bit can be cleared by writing 1 or by changing the polarity of edge detection.