Then, first of all, we should study the hardware to see if it can meet our requirements. In the UART chapter, the main control chip S3C2440 said that the baud rate can reach 1 15200 under the system clock, and then commented that if pclk reaches 60M, it can reach 92 1600, so I will increase the main frequency as he said, and by the way, increase Pclk. It was found that 92 1600 could not be realized at all. Although the baud rate of 230400 can pass, the bit error rate is very high and it is not used at all. Then I tried to raise the Pclk to 70M. In this way, the baud rate can be increased to 230400 and the transmission is stable, but higher baud rate cannot be realized and Pclk cannot be improved indefinitely, because our development board is still connected. In the case of Pclk70M, the touch screen is frequently restarted, indicating that this scheme is not feasible, so pass is dropped. Let me briefly talk about how I changed the system clocks FCLK, HCLK and PCLK. I won't go into details about the relationship and calculation method of these three clocks. I mainly refer to blog/view/13b4c686b9d528ea80c77904.html, and I found the file mach-smdk2440.c under linux, which defines the clk structure used by the serial port and is also the initialization configuration structure of the serial port when the linux system is started. But I changed this place and asked him to initialize the configuration. As the clock source of serial port, fclk is the first choice, but I find it is not feasible, so I will continue to look for it.
This leaves one function to consider, s3c24xx_serial_getclk (). When you enter this function, you will find that this function is a comprehensive configuration of serial clock and baud rate. Entering this function, there is a structure tmp_clksrc, which is very critical. His contents are as follows:
Static structure S3C24xx _ UART _ CLKSCRCTMP _ CLKSCRC = {
. name = "pclk "，
. Minimum porter
= 0,
. Max porter
= 0,
. divisor
= 1,
};
As can be seen from this name, it sets the clock source of the serial port to pclk, which is also the culprit. But when I changed my name to fclk, the whole system could not be started, including the initialization configuration in mach-smdk2440.c mentioned above. Later, I made a judgment when configuring serial port. When the baud rate is lower than 200000, the system source configuration remains unchanged. When the baud rate is higher than 200000, I don't use the structure tmp_clksrc, but use my own defined structure. Of course, I changed my name to fclk. I found that although only the clock source can change some parameters in it, the clock source is still pclk, which means that my changes have not taken effect at all. Because this linux call is too complicated, I will try it. There is no way out. After configuring the serial clock code, I added the following lines of code to directly change the register of S3C2440. I know it's immoral and easy to cause system confusion, but I just tried it and didn't expect it to be really useful.
Add in the samsung.c file
If (Potter & gt= 200000)
{
Printk ("Porter & gt = 200000 @ samsung.c \ n");
__raw_writel(0x 1fc5，s 3c 24 xx _ VA _ UART 0+s 3c 24 10 _ UCON)；
__raw_writel(0x0fc5，s 3c 24 xx _ VA _ UART 1+s 3c 24 10 _ UCON)；
__raw_writel(0x8fc5，s 3c 24 xx _ VA _ UART 2+s 3c 24 10 _ UCON)；
__raw_writel(32，s 3c 24 xx _ VA _ UART 0+s 3c 24 10 _ UCON+0x 24)； //Make sure that the baud rate of the console is still 1 15200 for display.
__raw_writel(3，s 3c 24 xx _ VA _ UART 1+s 3c 24 10 _ UCON+0x 24)； //92 1600
//__raw_writel(3，s 3c 24 xx _ VA _ UART 1+s 3c 24 10 _ UCON+0x 24)；
}
I got the above code through many experiments. Because the system master clock fclk used at the beginning was 400M, the UBRDIV 1 frequency division should be 3, but in this case, the bit error rate is high, and it is still impossible to transmit. So I finally understand why the manual says that pclk can achieve 92 1600 at 60M, because if calculated with 60M clock, the frequency division UBRDIV 1 is 3.069, which is the closest to integer 3, so the baud rate transmission of 92 1600 can be achieved at this bit error rate, so I set the system clock fclk to 420M, where MDL is. PDIV= 1, PDIV = 65438Ucon 1=0x0fc5, ucon2=0x8fc5, so n= 1+6=7, so the clock source of serial port is fclk/n=60M, and the accurate baud rate of 92/kloc-0 can be obtained. Therefore, to achieve my original goal, I can actually achieve other baud rates, such as 46088.
There is also a small idea to improve the baud rate of serial port. We can also use USB to serial port, because USB to serial port can achieve 92 1600. The driver of USB to serial port integrated in linux only needs to call the node of USB to serial port in the open function of calling serial port. Of course, I haven't tried this scheme, because we only have one USB port, which is also occupied. I hope friends in need can try it.